tiny-hdl

Hardware

hdl simulation

SHOW HN2021

122points
27comments
#424of 2,533 in 2021
Top 17%of 2021 by points

How HN took it

CuriousMostly questions and neutral comments

2 positive, 11 neutral or asking, 1 mixed, 0 critical, out of 14 comments about the project. Thread score +0.08.

Docs: 1 for, 0 againstIdea: 1 for, 0 against

The thread, comment by comment

Each row is a top-level comment and its replies, in HN's order. Select a cell to open that comment on HN.

positive neutral or mixed critical about another commenter or something else the maker

What HN said

What people liked

  • Impressive, fascinating work

    From 3 comments
    • Very impressive work. I've only spent about an hour going through this post and its predecessor. I'm a career software engineer, although I've been working very closely with a…
      brandmeyer on HN
    • Fascinating work, thanks for creating it!
      spfzero on HN
    • This is great! I also like your other posts in the series on tiny-hdl. Thank you for writing this up!
      i_don_t_know on HN

Objections

  • Formal verification may not catch Spectre-type timing issues

    From 2 comments
    • Spectre isn't really something that you can catch with formal verification. It sort of isn't a bug, that's why it's such a problem.
      mhh__ on HN
    • Only because most models focus on functionality, not on timing.
      amelius on HN

Requests

  • Write-up on place and route and netlist-to-layout algorithms

    From 1 comment
    • Can you do a write up on the lower level algorithms like place and route, circuit constraints solving optimization, the process from the netlist stage to autorouting? The…
      ampdepolymerase on HN

Questions

  • How signal updates propagate to sensitive processes and performance comparison

    From 2 comments
    • If using "signal of vector": how does an update is propagated to a process that is sensitive only to some particular bits? So, any update to that signal (whatever the bit) causes…
      artemonster on HN
    • In the "signal-of-vectors vs vector-of-signals" comparison, "vector" refers to the Racket data type used for arrays. It should not be confused with "bit vectors", which are…
      senshu on HN
  • Similar simple RISC-V cores in Clash or Bluespec

    From 1 comment
    • Cool! Is there a similarly simple core to compare with in Bluespec and Clash?
      mhh__ on HN

Alternatives named

  • Clash

    From 1 comment
    • In the "signal-of-vectors vs vector-of-signals" comparison, "vector" refers to the Racket data type used for arrays. It should not be confused with "bit vectors", which are…
      senshu on HN
  • Bluespec

    From 1 comment
    • Cool! Is there a similarly simple core to compare with in Bluespec and Clash?
      mhh__ on HN
  • SymbiYosys formal verification

    From 1 comment
    • While simulation is a well-established practice among digital hardware developers, I have the impression that formal verification is still largely ignored. I hope it changes as…
      _mouvantsillage on HN

Category, keywords, summaries and labels on this page were made by AI (Thread Reader v2) and not checked by hand. Each point links to the comments it came from.

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