Retrocomputing with Clash
Learning and science
hardware design book
SHOW HN2021
How HN took it
6 positive, 10 neutral or asking, 0 mixed, 3 critical, out of 19 comments about the project. Thread score +0.11.
Idea: 4 for, 1 againstExecution: 1 for, 2 against
The thread, comment by comment
Each row is a top-level comment and its replies, in HN's order. Select a cell to open that comment on HN.
positive neutral or mixed critical about another commenter or something else the maker
What HN said
What people liked
Clash is a better language than Verilog/VHDL for hardware design
From 2 comments
Clash is not pseudo, it's actual HDL. Right now it compiles to Verilog, yes, but this is minor a technicality. > the choice of HDL (which was 95% of the time, Verilog, for the…
gnull on HNI'm trying to look at one specific component here, the language itself. My claim is that as a language Clash is way better than SystemVerilog. True, Verilog has more mature…
gnull on HN
Debugging via high-level simulation is well covered in the book
From 1 comment
Debugging via high-level simulation is something my book spends a lot of time on. If you look at the sample chapters, you can see that the same Clash code can also be compiled…
gergoerdi on HN
Good Compucolor II chapter choice for the book
From 1 comment
It was an interesting choice to include the Compucolor II emulation. It was a very quirky machine with some interesting design choices, but not very popular. Ops website…
tasty_freeze on HN
Objections
Verilog/VHDL tooling and vendor support matter more than the language
From 3 comments
I am having trouble understanding the usefulness of all these new pseudo-HDL languages. In all the projects that I've worked on, the choice of HDL (which was 95% of the time,…
laydn on HNIt's not that we have a low standard, it's that we are bound by the full suite of tools that are provided to us in order to achieve our design objective. When I am close to…
laydn on HNAs the GP points out the problem you're up against is the tooling - to be mainstream a new language needs to be supported by the main commercial ASIC tool chains -…
Taniwha on HN
Clash ecosystem lacks vendor tool integration for tapeout
From 2 comments
As the GP points out the problem you're up against is the tooling - to be mainstream a new language needs to be supported by the main commercial ASIC tool chains -…
Taniwha on HNIt's not that we have a low standard, it's that we are bound by the full suite of tools that are provided to us in order to achieve our design objective. When I am close to…
laydn on HN
New HDLs seem unnecessary compared to Verilog
From 1 comment
I am having trouble understanding the usefulness of all these new pseudo-HDL languages. In all the projects that I've worked on, the choice of HDL (which was 95% of the time,…
laydn on HN
Requests
Explain Clash debug and design flow for Xilinx FPGAs
From 1 comment
But, HOW do you debug Clash? For example, what is the design and debug flow of using Clash to target a Xilinx FPGA? My guess is that you're going to tell me I will have to debug…
laydn on HN
Clarify how Clash relates to HLS and Chisel
From 2 comments
Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not "higher level" then VHDL or Verilog. In some…
rowanG077 on HNClash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling. HLS generally means you compile a very high level description of…
rowanG077 on HN
Questions
How does Clash compile to bitstream if it generates Verilog
From 1 comment
>Clash is not HLS i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?
tubby12345 on HN
Does Clash match HLS resource overhead
From 1 comment
qq: i know that for HLS sometimes (most?) the generated HDL is 10x the number of resources (flip-flops?) compared to hand-written HDL. how bad is clash in this respect?
tubby12345 on HN
Alternatives named
Chisel
From 2 comments
got it - it's like chisel. thanks
tubby12345 on HNLooking at your posting history I can be a little more concrete: Chisel is essentially a metaprogramming framework for VHDL/Verilog. Clash is a compiler closely based on GHC that…
rowanG077 on HN
Verilog and VHDL
From 1 comment
I am having trouble understanding the usefulness of all these new pseudo-HDL languages. In all the projects that I've worked on, the choice of HDL (which was 95% of the time,…
laydn on HN