jor1k
Dev tools
cpu emulator
SHOW HN2014
43points
8comments
#742of 2,272 in 2014
Top 33%of 2014 by points
How HN took it
QuietFewer than 5 comments about the project
1 positive, 1 neutral or asking, 0 mixed, 0 critical, out of 2 comments about the project.
Execution: 1 for, 0 against
The thread, comment by comment
Each row is a top-level comment and its replies, in HN's order. Select a cell to open that comment on HN.
positive neutral or mixed critical about another commenter or something else the maker
What HN said
What people liked
Impressive work and a cool project that is still thriving
From 1 comment
I think it was over a year ago that I hacked together the network support for this, submitted a few links to HN, Slashdot, and Reddit, and then proceeded to neglect it more or…
benjamincburns on HN
Objections
Multicore emulation runs in one worker thread with no performance gain yet
From 2 comments
Just some technical details: The cores are emulated in one worker thread because shared memory in threads is still not supported by the engines. You can use "htop" to see the…
s-macke on HNNot yet. But when shared memory arrays become available in Javascript it will be useful. But take a look here: http://s-macke.github.io/jor1k/compile.html So you can use it in a…
s-macke on HN
Requests
Performance improvement with SMP once shared memory arrays are available
From 2 comments
Is there any performance improvement on multithreaded tasks with SMP enabled?
benjamincburns on HNNot yet. But when shared memory arrays become available in Javascript it will be useful. But take a look here: http://s-macke.github.io/jor1k/compile.html So you can use it in a…
s-macke on HN
Questions
Does SMP mode improve performance on multithreaded tasks?
From 1 comment
Is there any performance improvement on multithreaded tasks with SMP enabled?
benjamincburns on HN
Alternatives named
RISC-V and its JavaScript emulator riscv-angel
From 2 comments
OpenRISC 2000 may end up converging on the RISC-V ISA. A blog post and accompanying comment[1] shed a bit of light on David Patterson (creator of the original RISC instruction…
otoburb on HNI am still fascinated by the sheer number of RISC CPUs out there. But more amazing than this is their similarity. I think we should develop a new (abstract) RISC CPU which…
s-macke on HN